The Intel 64 and IA-32 architectures provide mechanisms for managing andimproving the performance of multiple processors connected to the same systembus. These include:

Intel64 和IA-32架構提供管理和提升連接到相同系統總線多個處理器性能的機制。它包括：

• Bus locking and/or cache coherencymanagement for performing atomic operations on system memory.

•　總線鎖和／或緩存一致性管理，用於在系統內存執行原子操作

• Serializing instructions.

•指令序列化

• An advance programmable interruptcontroller (APIC) located on the processor chip (see Chapter 10,“AdvancedProgrammable Interrupt Controller (APIC)”). This feature was introduced by thePentium processor.

•　處理器芯片上有一個高級可編程中斷控制器(APIC)（見第10章，“高級可編程中斷控制器(APIC) ”）。這一特性在Pentium處理器被引入。

• A second-level cache (level 2, L2).For the Pentium 4, Intel Xeon, and P6 family processors, the L2 cache is includedin the processor package and is tightly coupled to the processor. For thePentium and Intel486 processors, pins are provided to support an external L2cache.

•二級緩存(L2)。Pentium4, IntelXeon, P6 家族的二級緩存包含在處理器封包內并緊密結合到處理器上。而在Pentium和Intel486處理器上，提供了針腳用於外接二級緩存。

• A third-level cache (level 3, L3).For Intel Xeon processors, the L3 cache is included in the processor package andis tightly coupled to the processor.

•　三級緩存(L3)。Intel Xeon處理器的三級緩存包含在封包內并緊密結合到處理器上。

• Intel Hyper-Threading Technology.This extension to the Intel 64 and IA-32 architectures enables a single processorcore to execute two or more threads concurrently (see Section 8.5, “Intel Hyper-Threading Technology and Intel Multi-Core Technology”).

•Intel 超線程技術。這一對Intel 64 和IA-32架構的擴展，使得單個處理核心可以同時執行2個或更多的線程（見8.5，“Intel 超線程技術和Intel多核技術”）。

Thesemechanisms are particularly useful in symmetric-multiprocessing (SMP) systems.However, they can also be used when an Intel 64 or IA-32 processor and aspecial-purpose processor (such as a communications, graphics, or video processor)share the system bus. These multiprocessing mechanisms have the followingcharacteristics:

•　這些機制對對稱多處理器(SMP)系統非常有用。然而，它也可以用於 Intel 64 或者IA-32 處理器和特殊用途的處理器（比如通信、圖形或者視頻處理器）共享系統總線的時候。這些多處理機制有以下特性：

• To maintain systemmemory coherency — When two or more processors are attemptingsimultaneously to access the same address in system memory, some communicationmechanism or memory access protocol must be available to promote data coherencyand, in some instances, to allow one processor to temporarily lock a memorylocation.

•　保持系統內存一致—— 當2個或者多個處理器視圖同時訪問相同系統內存地址的時候，某些通信機制或者內存訪問協議需要保證資料一致，並且，在某些情況，允許一個處理器臨時鎖定內存地址。

• To maintain cache consistency — When oneprocessor accesses data cached on another processor, it must not receiveincorrect data. If it modifies data, all other processors that access that datamust receive the modified data.

•　保持緩存一致 —— 當一個處理器訪問另一個處理器的緩存資料的時候，它應該要得到正確的資料。如果它修改資料，所有訪問這段資料其他處理器需要得到修改後的資料。

• To allow predictable ordering of writes to memory— In some circumstances, it is important that memory writes beobserved externally in precisely the same order as programmed.

•　允許可預測循序寫內存——在某些情況，它非常重要。比如外部寫內存要精確的與編程順序一致。

• To distribute interrupt handling among a group ofprocessors — When several processors are operating in a system in parallel, itis useful to have a centralized mechanism for receiving interrupts anddistributing them to available processors for servicing.

•　在一組處理器中分配中斷操作——當多個處理器在系統中並行運作，它被作為集中處理機制接收中斷并分配它們到可用處理器。

• To increase system performance by exploiting themulti-threaded and multi-process nature of contemporary operating systems andapplications. The caching mechanism and cache consistency of Intel 64 and IA-32processors are discussed in Chapter 11. The APIC architecture is described inChapter 10. Bus and memory locking, serializing instructions, memory ordering, andIntel Hyper-Threading Technology are discussed in the following sections.

• 　通過利用現代操作系統和應用的多線程和多處理器能力來提高系統性能 —— Intel64 和 IA-32 處理器的緩存和緩存一致性機制在第 11 章討論。 APIC 架構在第 10 章討論。總線和內存所，指令序列化，內存順序，和 Intel 超線程技術在後續章節介紹。